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DATA SHEET
MOS INTEGRATED CIRCUIT
PD7566A, 7566A(A)
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD7566A is a product of the PD7554, 7564 sub-series which is a low-end, low-cost version of the PD7500 series microcomputers. This 4-bit single-chip microcomputer has fewer ports than the other products in the PD7500 series, in order to reduce the package size, and is especially ideal for temperature control applications, as well as for application systems, such as air conditioners, microwave ovens, refrigerators, rice cooker, washing machines, and cassette deck controllers. Some of the output pins for the microcomputer can be used to directly drive triacs and LEDs. In addition, various I/O circuits can be selected by mask options, so that the number of necessary external circuits can be significantly reduced. A detailed function description is provided in the following user's manual. Be sure to read this manual when designing your system. PD7556, 7566 User's Manual: IEM-1111D
FEATURES
* 45 instructions (subset of the PD7500H SET B) * Instruction cycle: 2.86 microseconds (700 kHz, at 5V) with ceramic oscillator * Program memory (ROM): 1,024 words x 8 bits * Data memory (RAM): 64 words x 4 bits * Test sources: 1 external and 1 internal * 8-bit timer/event counter * 19 I/O lines (total output current: 100 mA) . Five pins can be used to directly drive triacs and LEDS : P80 to P82, P90 to P91 . Eight pins can be used to directly drive LEDs : P100 to P103, P110 to P113 . Four comparator input pins: P10/Cin 0 to P13/Cin 3 . Mask option functions available on all ports * Standby functions (STOP/HALT) * Data memory contents can be retained on a low voltage * Internal ceramic oscillator for system clock oscillation * CMOS * Low-power dissipation * Single power source (2.7 to 6.0V) APPLICATIONS
PIN CONFIGURATION (Top View)
P00/INT0 P01/Vref P10/Cin0 P11/Cin1 P12/Cin2 P13/Cin3 P80 P81 P82 CL2 CL1 VDD
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VSS P91 P90 P113 P112 P111 P110 P103 P102 P101 P100 RESET
PD7566A
5
PD7566A
: Air conditioner, microwave oven, refrigerator, audio equipment controller, etc. PD7566A(A) : Automotive and transportation equipments, etc. The quality level and absolute maximum ratings of the PD7566A and the PD7566A(A) differ. Except where specifically noted, explanations here concern the PD7566A as a representative product. If you are using the PD7566A(A), use the information presented here after checking the functional differences.
The information in this document is subject to change without notice. The 5 mark shows major revised points.
Document No. IC-2478D (O. D. No. IC-7885D) Date Published December 1994 P Printed in Japan
(c)
1994 1989
PD7566A, 7566A(A)
ORDERING INFORMATION
Part Number Package 24-pin plastic shrink DIP (300 mil) 24-pin plastic SOP (300 mil) 24-pin plastic shrink DIP (300 mil) 24-pin plastic SOP (300 mil) Quality Grade Standard Standard Special Special
PD7566ACS-xxx PD7566AG-xxx
5 5
PD7566ACS(A)-xxx PD7566AG(A)-xxx
Caution Be sure to specify mask options when placing your order. Remark xxx indicates ROM code number.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
PD7566A BLOCK DIAGRAM
INT0/P00
CLOCK CONTROL CL
CP
TIMER/ EVENT COUNTER
INTT
TEST CONTROL
PORT0 BUFFER
P00/INT0 P01/Vref
PC(10)
ALU(4)
C
A(4)
PORT1 BUFFER /COMPARATOR
4
P10/Cin0 - P13/Cin3
H(2) PROGRAM MEMORY 1024X8 BITS
L(4)
PORT8 LATCH BUFFER
3
P80 - P82
INSTRUCTION DECODER
SP(6)
PORT9 LATCH BUFFER
2
P90, P91
CL
O DATA MEMORY 64X4 BITS STANDBY CONTROL
PORT10 LATCH BUFFER
PD7566A, 7566A(A)
4
P100 - P103
SYSTEM CLOCK GENERATOR
PORT11 LATCH BUFFER
4
P110 - P113
CL1
CL2
VDD
VSS
RESET
3
PD7566A, 7566A(A)
CONTENTS
1.
PIN FUNCTIONS ...............................................................................................................................
1.1 1.2 1.3 1.4 1.5 1.6 1.7 PORT FUNCTIONS ................................................................................................................................. OTHER FUNCTIONS ............................................................................................................................... MASK OPTIONS FOR PINS ................................................................................................................... NOTES ON USING THE P00/INT0, AND RESET PINS ......................................................................... PIN I/O CIRCUITS ................................................................................................................................... RECOMMENDED PROCESSING OF UNUSED PINS............................................................................ I/O PORT OPERATIONS .........................................................................................................................
6 6 6 7 7 8 10 11
2.
INTERNAL FUNCTIONAL BLOCKS .................................................................................................
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 PROGRAM COUNTER (PC) .................................................................................................................... STACK POINTER (SP) ............................................................................................................................ PROGRAM MEMORY (ROM) ................................................................................................................. GENERAL-PURPOSE REGISTERS ......................................................................................................... DATA MEMORY (RAM) ......................................................................................................................... ACCUMULATOR (A) ............................................................................................................................... ARITHMETIC LOGIC UNIT (ALU) .......................................................................................................... PROGRAM STATUS WORD (PSW) ....................................................................................................... SYSTEM CLOCK GENERATOR ............................................................................................................. CLOCK CONTROL CIRCUIT ................................................................................................................... TIMER/EVENT COUNTER ...................................................................................................................... TEST CONTROL CIRCUIT ......................................................................................................................
13 13 14 15 15 16 17 17 17 18 19 20 21
3.
STANDBY FUNCTIONS ...................................................................................................................
3.1 3.2 3.3 3.4 3.5 STOP MODE ........................................................................................................................................... HALT MODE ............................................................................................................................................ RELEASING STOP MODE BY USING RESET INPUT........................................................................... RELEASING HALT MODE BY USING TEST REQUEST FLAGS .......................................................... RELEASING HALT MODE BY USING RESET INPUT ...........................................................................
22 22 22 22 23 23
4.
RESET FUNCTION ............................................................................................................................
4.1 INITIALIZATION ......................................................................................................................................
24 24
5. 6 7. 8. 9.
4
INSTRUCTION SET .......................................................................................................................... ELECTRICAL SPECIFICATIONS ....................................................................................................... CHARACTERISTIC DATA ................................................................................................................. APPLICATION CIRCUITS ................................................................................................................. PACKAGE DRAWING .......................................................................................................................
25
30
36
38
43
PD7566A, 7566A(A)
10. RECOMMENDED PC BOARD PATTERN FOR SOP (REFERENCE) ................................................ 11. RECOMMENDED SOLDERING CONDITIONS ................................................................................ APPENDIX A. COMPARISON FOR PD7566A SUB-SERIES PRODUCTS........................................... APPENDIX B. DEVELOPMENT SUPPORT TOOLS ............................................................................... APPENDIX C. RELATED DOCUMENTS .................................................................................................
47
48
49
50
55
5
5
PD7566A, 7566A(A)
1.
1.1
PIN FUNCTIONS
PORT FUNCTIONS Pin Name Input/ Output Shared with: I/O Circuit Type S Input T 4-bit input port (PORT 1) Input U
Function
At Reset
P00 Input P01 P10-P13 Input
INT0 Vref Cin0 Cin3 -
2-bit input port (PORT 0). P00 is also used to input count clocks (event pulses).
P80-P82
Output
3-bit output port (PORT 8). High-current (15 mA), and medium-voltage (9V) output 2-bit output port (PORT 9). High-current (15 mA), and medium-voltage (9V) output 4-bit I/O port (PORT 10). Medium-current (10 mA), and medium-voltage (9V) I/O 4-bit I/O port (PORT 11). Medium-current (10 mA), and medium-voltage (9V) I/O
High impedance
O
P90, P91
Output
-
P100 P103 P110P113
Input/ Output Input Output
-
-
High impedance or highlevel output
P
1.2
OTHER FUNCTIONS Pin Name Input/ Output Shared with: I/O Circuit Type S
Function
At Reset
INT0
Input
P00
Edge-detecting testable input pin (rising edge) Comparator reference voltage input pin (Whether this pin is used as P01 or as Vref is specified by a mask option.)
Input
Vref
Input
P01
Input
T
Cin0-Cin3
Input
4-bit comparator input pins (Whether these P10-P13 pins are used as digital input pins (P10 to P13) or as comparator input pins (Cin0 to Cin3) is specified by the mask option for each bit. A ceramic oscillator is connected across these pins.
Input
U
CL1 CL2
RESET
System reset input pin (high-level active). A pull-down resistor can be interconnected to this pin by a mask option. Power pin GND pin
R
VDD VSS
6
PD7566A, 7566A(A)
1.3 MASK OPTIONS FOR PINS The following mask options are available. These mask options can be selected in bit units. Pin Name P00 P01/Vref Mask Option No internally provided resistor Pull-down resistor internally provided Pull-up resistor internally provided External Vref input No internally provided resistor (CMOS input) Pull-down resistor internally provided (CMOS input) Pull-up resistor internally provided (CMOS input) Comparator input No internally provided register Pull-down resistor internally provided (CMOS input) Pull-up resistor internally provided (CMOS input) Comparator input No internally provided register Pull-down resistor internally provided (CMOS input) Pull-up resistor internally provided (CMOS input) Comparator input No internally provided register Pull-down resistor internally provided (CMOS input) Pull-up resistor internally provided (CMOS input) Comparator input No internally provided register Pull-down resistor internally provided (CMOS input) Pull-up resistor internally provided (CMOS input) N-channel open-drain output N-channel open-drain output N-channel open-drain output N-channel open-drain output N-channel open-drain output CMOS (push-pull) output CMOS (push-pull) output CMOS (push-pull) output CMOS (push-pull) output CMOS (push-pull) output
5
P10/Cin0
P11/Cin1
P12/Cin2
P13/Cin3
P80 P81 P82 P90 P91 P100 P101 P102 P103 P110 P111 P112 P113 RESET Internal Vref Note setting
N-channel open-drain I/O Push-pull I/O N-channel open-drain I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain I/O with pull-up resistor internally provided Pull-down resistor is not internally provided Pull-down resistor is internally provided Internal bias is not provided A 1/2 VDD internal bias is applied to Vref
Note When any of pins P10-P13 is specified as " comparator", and " internal bias is not provided" is specified for the internal Vref setting, specify " external Vref input" for pin P01. When none of pins P10-P13 is specified as " comparator", specify " internal bias is not provided" for the internal Vref setting. There is no mask option for PROM products. For more information, see the PD75P66 Data Sheet (IC-7518). 7
PD7566A, 7566A(A)
1.4
NOTES ON USING THE P00/INT0, AND RESET PINS
In addition to the functions described in 1.1, 1.2, and 1.3, an exclusive function for setting the test mode, in which the internal functions of the PD7566A are tested, is provided to the P00/INT0 and RESET pins. If a voltage less than VSS is applied to either of these pins, the PD7566A is put into test mode. Therefore, even when the PD7566A is in normal operation, if noise less than the VSS is input into any of these pins, the PD7566A will enter the test mode, and this will cause problems for normal operation. As an example, if the wiring to the P00/INT0 pin or the RESET pin is long, stray noise may be picked up and the above mentioned problem may occur. Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below. * Connect a diode having a low VF across P00/INT0 and RESET, and VSS.
VDD
* Connect a capacitor across P00/INT0 and RESET, and VSS.
VDD
VDD P00/INT0, RESET Low VF diode
VDD P00/INT0, RESET
VSS
VSS
8
PD7566A, 7566A(A)
1.5 PIN I/O CIRCUITS Schematic drawings of the I/O circuits for the microcomputer's pins are shown below. (1) Type O
VDD
data
P-ch
Mask option OUT N-ch (medium-voltage, high current)
output disable
(2) Type P
VDD
data
P-ch
Mask option
IN/OUT
output disable
N-ch (medium-voltage, high-curren
Medium-voltage, input buffer
(3) Type R
Mask Option
9
PD7566A, 7566A(A)
(4) Type S
VDD
Mask Option
IN
(5) Type T
VDD
Mask option IN VDD Rref
+
Mask option
Rref
(6) Type U
VDD
Mask option
+
IN
Reference voltage
10
PD7566A, 7566A(A)
1.6 RECOMMENDED PROCESSING OF UNUSED PINS Pin P00/INT0 P01/Vref Connect to VSS or VDD P10-P13 P80-P82 Open P90, P91 P100-P103 P110-P113 Input : Connect to VSS or VDD Output: Open Recommended Processing Connect to VSS
11
PD7566A, 7566A(A)
1.7
I/O PORT OPERATIONS (1) P00, P01 (Port 0) Port 0 is a 2-bit input port and consists of pins P00 and P01. These pins are multiplexed, and P00 can also input count clocks or testable signal (INT0), while P01 is used, when so specified by a mask option, to input a reference voltage (Vref) to the internal comparator. To input a count clock from P00, set bits 2 and 1 (CM2 and 1) for the clock mode register to "01" (see 2.10, Clock Control Circuit). To allow P00 to serve as INT0, set the SM3 flag to 1. Whether P01 is used to input a reference voltage (Vref) to the comparator is specified by a mask option. In this case, the port function for the P01 pin cannot be used. The data on P00 and P01 can be loaded to the lower 2 bits (A0 and A1) of the accumulator at any time, by executing a port input instruction (IPL, L = 0). (2) P10/Cin 0 to P13/Cin 3 (Port 1) Port 1 is a 4-bit input port consisting of these four pins, which can also be used to input analog voltages to the comparator, when so specified by mask options. To input analog voltages through Port 1, a comparator must be connected to each bit of the port by a mask option, and a port input instruction (IPL, L = 1) must be executed. The analog voltage input through these pins to the comparator is always compared with a reference voltage input through the Vref pin. It takes up to 3 machine cycles to accomplish this comparison. Therefore, to change the voltage applied to the Vref pin by port output to form an A/D converter by using a resistor ladder, wait for 3 machine cycles after executing a port output (OPL) instruction. Then carry out an input (IPL, L = 1) instruction to obtain the result of the comparison. If the output instruction is executed during a 3 machine cycle period that precedes the IPL instruction (L = 1), which inputs the comparison result, the comparator accuracy may be degraded. For this reason, do not execute the OPL instruction during 3 machine cycles immediately before the IPL instruction is executed. Example: LHLI OPL NOP NOP LHLI IPL 1 ; L=1 ; Input of comparison result 0AH ; L = 10 ; Port 10 output (Vref is changed)
(3) P80 to P82 (Port 8), and P90 to P91 (Port 9) Pins 80 to P82 constitute a 3-bit output port with output latch, Port 8, while P90 to P91 form a 2-bit output port with output latch, Port 9. When a port output instruction (OPL, L = 8, or L = 9) is executed, the contents of the accumulator are latched on the output latches, and, at the same time, output to these ports. Each bit in Ports 8 and 9 can be set or reset by SPBL or RPBL instruction. Two output modes can be selected for Ports 8 and 9 by a mask option: CMOS (push-pull) or N-channel open-drain mode. The N-channel open-drain output mode is useful for interfacing a circuit operating on a supply voltage different from that to the microcomputer, because the output buffer in this mode can withstand an applied 9V.
12
PD7566A, 7566A(A)
(4) P100 to P103(Port 10), and P110 to P113 (Port 11)..........Pseudo-bidirectional I/O Pins P100 to P103 constitute a 4-bit I/O port with output latches, Port 10, while P110 to P113 form Port 11, which is a 4-bit I/O port with output latches. When a port output instruction (OPL, L = 10 or L11) is executed, the accumulator contents are latched to the output latches and, at the same time, output to either of these ports. Data once written to the output latch and the state of the output buffer are retained until an output instruction that manipulates Port 10 or 11 is executed next, or until the RESET signal is input. Therefore, the states of the output latches and output buffer will not be changed, even when an input instruction is executed to these ports. Each bit of Ports 10 and 11 can be set or reset by SPBL or RPBL instruction. Three input modes can be selected for Ports 10 and 11 by mask options: N-channel open-drain I/O, N-channel open-drain I/O with pull-up resistors connected, and CMOS (push-pull) modes. The N-channel open-drain mode is useful for interfacing a circuit operating on a supply voltage different from that fed to the microcomputer, because the I/O buffer in this mode can withstand a 9V application. If the CMOS (push-pull) I/O mode has been selected and an output instruction has once been executed, the ports cannot return to the input mode. However, the pin states can be checked by executing a port input (IPL) instruction. In the N-channel open-drain mode, regardless of whether the pull-up resistors are connected or not, the ports are set in the input mode, when high-level signals are output to them, and the data on the 4 bits of each port can be loaded to the accumulator. Thus, the port serves as a pseudo-bidirectional port. The three I/O modes are selected under the following conditions: CMOS I/O i) To use all the 4-bits as input port pins ii) To use port pins as output pins from which no medium-voltage output is required N-channel open-drain I/O i) To use port pins in applications where inputting outputting a medium-voltage is required ii) To use some port pins as input pins and the others as output pins iii) To alternately input and output data through one port pin N-channel open-drain I/O with pull-up resistor connected i) To use some port pins as input pins and the other, as output pins in applications where pull-up resistors are required ii) To alternately input and output data through one port pin in application where a pull-up resistor is required Caution To use port pins as input pins in modes and above, it is necessary to write "1" to the output latch in advance and to turn off the N-channel transistor.
13
PD7566A, 7566A(A)
2.
2.1
INTERNAL FUNCTIONAL BLOCKS
PROGRAM COUNTER (PC) ...... 10 BITS This is a 10-bit binary counter that retains the address information for the program memory (ROM).
Fig. 2-1 Program Counter
PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC
Normally, each time an instruction has been executed, the PC contents are automatically incremented by the number of bytes for the instruction. When a call instruction has been executed, the current contents of the PC (i.e., return address) are saved to the stack, and a new call address is loaded to the PC. When a return instruction has been executed, the contents of the stack (i.e., return address) are loaded to the PC. When a jump instruction has been executed, immediate data that indicates the jump destination is loaded to some or all of the bits for the PC. When a skip instruction has been executed, the PC contents are incremented by 2 or 3 during 1 machine cycle, depending on the number of bytes for the instruction to be executed next. All the PC bits are cleared to 0, when the RESET signal has been input.
14
PD7566A, 7566A(A)
2.2 STACK POINTER (SP) ...... 6 BITS This is a 6-bit register. When port of the data memory is used as a last-in, first-out (LIFO) stack area, the SP retains the first address for the stack.
Fig. 2-2 Stack Pointer
SP5 SP4 SP3 SP2 SP1 SP0 SP
The SP contents are decremented when a call instruction has been executed, and are incremented when a return instruction has been executed. To obtain a stack area, the SP must be initialized by TAMSP instruction. Note, however, that 0 is is unconditionally loaded to the LSB for the SP (i.e., bit SP0) when TAMSP instruction has been executed. Stacking operation begins with decrementing the SP contents. Therefore, the highest address for the stack area +1 is set in the SP. If the highest address for the stack area is 3FH, which is the highest address in the data memory, the initial values for the SP5 to 0 bits must be 00H. However, keep the data to be stored in AM to 40H when TAMSP instruction is executed, so that the microcomputer can be easily emulated by PD7500H (EVAKIT-7500B).
Fig. 2-3 Executing TAMSP Instruction
A3 A2 A1 A0 (HL)3 (HL)2 (HL)1 (HL)0 0 SP5 SP4 SP3 SP2 SP1 SP0
The SP contents cannot be read. Caution The SP contents are undefined, when the RESET signal has been input. Therefore, make sure that the SP is initialized at the beginning of the program. Example: LHLI LAI ST LAI TAMSP 4 ; SP = 40H 00H 0
15
PD7566A, 7566A(A)
2.3
PROGRAM MEMORY (ROM) ...... 1,024 WORDS X 8 BITS This is a mask programmable ROM, consisting of 1,024 words by 8 bits. The ROM is addressed by the program
counter (PC). The program is stored in the program memory. Address 000H in this memory is a reset start address.
Fig. 2-4 Program Memory Map
(0) 000H Reset start
(1023) 3FFH
2.4
GENERAL-PURPOSE REGISTERS Two general-purpose registers, H (2 bits) and L (4 bits), are available. Each of these registers can be manipulated
independently from the other. In addition, these registers can be used as a pair register (HL). The pair register serves as a data pointer to address the data memory.
Fig. 2-5 General-Purpose Registers
1 H 0 3 L 0
The L register is also used to specify an I/O port or mode register, when an input/output instruction (IPL or OPL) is executed. This register is also used to specify the port bit to be set or reset by SPBL or RPBL instruction.
16
PD7566A, 7566A(A)
2.5 DATA MEMORY (RAM) ...... 64 WORDS X 4 BITS The data memory is static RAM configured of 64 words by 4 bits, and is used to store various data and as a stack area. The data memory is also used in pairs with the accumulator, making it possible to process 8-bit data.
Fig. 2-6 Data Memory Map
(0) 00H
64 words x 4 bits
(63) 3FH
The data memory can be addressed in the following three addressing modes: * * * Direct: In this mode, the data memory is directly addressed by the immediate data for an instruction. Register indirect: The data memory is indirectly addressed by the contents of pair register HL (including autoincrement and autodecrement). Stack: The data memory is indirectly addressed by the contents of the stack pointer (SP).
Any space in the data memory can be used as stack. The boundary of the stack is determined by initializing the SP by TAMSP instruction. After that, the stack area is automatically accessed by call and return instructions. When a call instruction is executed, the contents of the PC and program status word (PSW) are stored in stack, as illustrated below. Stack area 3 SP - 4 SP - 3 SP - 2 SP - 1 0 0 PC9
Note
0 PC8 PSW
PC3 - PC0 PC7 - PC4 Note Bit 1 of PSW is always 0.
When a return instruction has been executed, the PC contents are restored, but the PSW contents are not. The data memory contents can be retained on a low supply voltage in the STOP mode.
17
PD7566A, 7566A(A)
2.6
ACCUMULATOR (A) ...... 4 BITS This is a 4-bit register which plays a central role, when an arithmetic operation is performed. The accumulator
can also be used in pairs with a data memory address, indicated by pair register HL, to process 8-bit data.
Fig. 2-7 Accumulator
A3 2.7 A2 A1 A0 A
ARITHMETIC LOGIC UNIT (ALU) ...... 4 BITS This is a 4-bit arithmetic operation circuit that carries out operations such as binary addition, logic operations,
increment, decrement and comparison, as well as bit manipulation. 2.8 PROGRAM STATUS WORD (PSW) ...... 4 BITS The PSW consists of two skip flags (SK1 and SK0) and a carry flag (C). Bit 1 of this register is always 0.
Fig. 2-8 Program Status Word
3 SK1 (1) Skip flags (SK1 and SK0) These flags retain the following skip conditions: * String effect by LAI instruction * String effect by LHLI instruction * Establishment of skip conditions by instructions other than string-effect instructions The skip flags are automatically set or reset each time an instruction has been executed. (2) Carry flag (C) This flag is set to 1, when an addition instruction (ACSC) is executed, and a carry is consequently generated from the bit 3 of the ALU. If a carry is not generated, the carry flag is cleared to 0. In addition, the carry flag can also be set by SC instruction, and cleared by RC instruction. The content of the flag can be tested by SKC instruction. The PSW contents are automatically stored in the stack area when a call instruction is executed, and are not restored even when a return instruction is implemented. When the RESET signal is input, the SK1 and SK0 flags are cleared to 0, and the C flag content becomes undefined. 2 SK0 1 0 0 C PSW
18
PD7566A, 7566A(A)
2.9 SYSTEM CLOCK GENERATOR
The system clock generator consists of a ceramic oscillator, a 1/2 frequency divider, standby mode (STOP/HALT) control circuit, and other circuits. The ceramic oscillator can oscillate, when an external ceramic oscillator is connected across pins CL1 and CL2. The signal output by the internal ceramic oscillator is a system clock (CL), which is then divided in two to create a CPU clock (o). The standby mode control circuit mainly consists of a STOP flip-flop and HALT flip-flop. The STOP flip-flop is set by a STOP instruction, stopping the clock supply. When the ceramic oscillator is operating, this flip-flop stops the oscillator, setting the microcomputer in the STOP mode. The STOP flip-flop is reset when a high-level RESET signal is input. As a result, the ceramic oscillator resumes its operation, and the clocks supply is started, when the RESET signal later goes low. The HALT flip-flop is set by a HALT instruction, disabling the input of the 1/2 frequency divider, which generates CPU clock o, and thereby stopping only CPU clock o (HALT mode). The HALT flip-flop is reset by the HALT RELEASE or the falling of RESET input (which becomes active when one of the test request flags has been set), allowing the supply of o to be started. The HALT flip-flop remains set even while the RESET signal is active (high-level), and operates in the same manner as in the HALT mode. When Power-ON Reset is performed, the ceramic oscillator starts at the rising edge of the RESET signal. After the oscillator has started, however, a specific period is required for the oscillator to stabilize. To present the CPU from malfunctioning due to anstable clock, the HALT flip-flop is set to suppress the CPU clock o while the RESET signal is high. Therefore, the high-level width of the RESET signal must be greater than the time required for the ceramic oscillator you use to stabilize.
Fig. 2-9 System Clock Generator
STOP F/F Q S HALT F/F Oscillation stops CL1 Ceramic oscillator CL2 R Q S HALT
Note
STOP
Note
RESET (high) R HALT RELEASE RESET ( RESET (
1/2
) )
o (to CPU)
CL (System clock)
Note indicates that an instruction has been executed.
19
PD7566A, 7566A(A)
2.10
CLOCK CONTROL CIRCUIT
The clock control circuit consists of a 2-bit clock mode register (made up of bits CM2 and 1), three prescalers (1, 2, and 3), and a multiplexer. This circuit inputs the output from the system clock generator (i.e., CL). An event pulse (from pin P00) selects a clock source and prescaler, as specified by the clock mode register, and supplies a count pulse (CP) to the timer/event counter.
Fig. 2-10 Clock Control Circuit
Internal Bus OPL CM2 CM1
Note
CL
PRESCALER 1 (1/4)
PRESCALER 2 (1/8)
PRESCALER 3 (1/8)
P00 CP
Note indicates that an instruction has been executed. A code is set in the clock mode register by an OPL (L = 12) instruction.
Fig. 2-11 Clock Mode Register Format
CM2 CM1 Clock mode register CM2 CM1 0 0 1 1 0 1 0 1 Count pulse frequency (CP) CL x 1/256 P00 CL x 1/32 CL x 1/4
Caution When setting a code in the clock mode register by the OPL instruction, be sure to clear the bit 0 (which corresponds to CM0 of EVAKIT-7500B (PD7500) during emulation) for the accumulator to 0.
20
PD7566A, 7566A(A)
2.11 TIMER/EVENT COUNTER
The timer/event counter mainly consists of an 8-bit count register.
Fig. 2-12 Timer/Event Counter
Internal bus
Note
TCNTAM
8 Count pending circuit
CP
8-BIT COUNT REG CLR TIMER RESET
Note
INTT (to test control circuit)
Note indicates that an instruction has been executed. The 8-bit count register is a binary up-counter. The contents of this counter are incremented each time a count pulse (CP) is input to the counter, and are cleared to 00H when TIMER instruction has been executed, when the RESET signal has been input, or when overflow (i.e., counting from FFH to 00H) has occurred in the counter. The following four count pulses can be selected by the clock mode register (see 2.10 Clock Control Circuit). CP: CL x 1 4 , CL x 1 1 , CL x , P00 32 256
The count register always counts up as long as the count pulse is input to it. Therefore, the TIMER instruction clears the contents of the count register to 00H and triggers a timer operation. The count register contents are incremented in synchronization with CP (or the rising edge of the P00 signal, when an external clock is selected). When the number of counts reaches 256, the count value is returned from FFH to 00H. At this time, the count register generates an overflow signal (INTT), setting the INTT test flag (INTT RQF). The count register then starts counting up from 00H. Whether or not an overflow has occurred can be learned by testing the INT RQF flag, using the SKI instruction. When the timer/event counter operates as a timer, the reference time for the timer is determined by the CP frequency. The accuracy of the measured time is determined, when the system clock is selected, by the system clock oscillation frequency. If the signal input through the P00 pin is selected as the clock, the accuracy is determined by the frequency of the signal input to the P00 pin. The contents of the count register can always be made ready by TCNTAM instruction. By using this instruction, the current time for the timer can be checked, or it can be determined how many event pulses have been generated so far by inputting the event pulses to the P00 pin and counting them (event counter operation). The count pending circuit is to ignore changes in the count pulses (CPs) while TCNTAM instruction is executed. This is necessary because, when TCNTAM instruction is used to read the contents of the count register, unstable data may be read while the present count is being updated. The timer/event counter operates using the system clocks (CL) or the signals input to the P00 pin as count pulses. Therefore, the timer/event counter can be used to release the HALT mode, in which the supply of the CPU clock o is stopped (see 3. STANDBY FUNCTIONS).
21
PD7566A, 7566A(A)
2.12
TEST CONTROL CIRCUIT
The test control circuit consists of two test flags, a flag called SM3, and a test request flag control circuit. The test request flags, INT0 RQF and INTT RQF, are set by two kinds of test sources (external test input (INT0) and timer overflow (INTT)). The SM3 flag determines whether or not inputting signals to the INT0 pin is enabled. The test request flag control circuit checks the contents of the test request flags, when an SKI instruction is executed, and resets the flags. The SM3 flag is set by an OPL (L = 0FH) instruction (corresponding to A3). When this flag is 1, the INT0 input is enabled. The INT0 RQF flag is set when the rising edge is detected on the INT0 pin, and is reset by an SKI instruction. The INTT RQF flag is set when an overflow occurs in the timer, and is reset by an SKI or TIMER instruction. The signals output by the test request flags are used to release the HALT modes. If one of or both the flags were to be set, the HALT modes are released. When the RESET signal is input, both the test request flags and SM3 flag are reset. Therefore, INT0 input is disabled as the initial condition after the RESET signal has been applied.
Fig. 2-13 Test Control Circuit
Internal bus OPL Note SM3 SKI
Note
TEST RQF CONTROL
INTT
NONSYNC EDGE GATE TIMER Note
S R
INTT RQF
Q
INT0
NONSYNC EDGE GATE
S R
INT0 RQF
Q
HALT RELEASE
Note indicates that an instruction has been executed.
22
PD7566A, 7566A(A)
3. STANDBY FUNCTIONS
The PD7566A can be set in two standby modes (STOP and HALT), in which the power dissipation for the microcomputer can be reduced while the program stands by. The STOP mode is set by a STOP instruction, while the HALT mode is set by a HALT Instruction. In the STOP mode, the supply of all the clocks is stopped, but the supply of only the CPU clock o is stopped in the HALT mode. When the HALT mode is set, program execution is stopped, but the contents of all the registers and data memory, immediately before the HALT mode has been set, are retained. The timer/event counter can operate even in the HALT mode. The STOP mode is released only by the input of the RESET signal. The HALT mode can be released by setting either or both the test request flags (INTT RQF and INT0 RQF), or by inputting the RESET signal. Therefore, the standby mode cannot be set, even when the STOP or HALT instruction is executed while one of the test request flags is set. To set the standby mode, when it is possible that one of the test request flags is set, execute an SKI instruction in advance to reset the test request flag. 3.1 STOP MODE The STOP mode can be set any time by executing the STOP instruction, unless either or both the test request flags are set. In this mode, the data memory contents are retained, but all other functions are stopped and become invalid, except for the RESET signal, which is used to release the STOP mode. Consequently, the power dissipation for the microcomputer is minimized. Caution In the STOP mode, the CL1 pin is internally short-circuited to VDD (high level) to prevent the leakage current from the ceramic oscillator. 3.2 HALT MODE In this mode, only the 1/2 frequency divider for the system clock generator is stopped. Consequently, the supply of system clock (CL) is not stopped and only the CPU clock (o) is stopped. The operation of the CPU, which calls for the CPU clock, is therefore stopped. However, the clock control circuit is not stopped. The clock control circuit can therefore input the CL signal generated by the system clock generator and event pulses input from an external source through the P00 pin, can supply both the clocks to the timer/event counter as count pulses (CPs). The timer/event counter can therefore operate on both the count pulses and its operation will not be interrupted. 3.3 RELEASING STOP MODE BY USING RESET INPUT When the RESET signal becomes high in the STOP mode, the HALT mode is set, and at the same time, ceramic oscillation starts. When the RESET signal goes low, the HALT mode is released followed by ordinary RESET operation. After that, the CPU starts executing the program from address 0. The STOP mode is thus released. The contents of the data memory are retained even while the mode is released, that the contents of registers become undefined.
23
PD7566A, 7566A(A)
Fig. 3-1 STOP Mode Release Timing
STOP instruction
RESET input
STOP mode
HALT mode (oscillator stabilization time)
Released Ordinary reset operation (execution starts from address 0)
Clock oscillation starts
Caution The STOP mode is not released by setting the test request flags. 3.4 RELEASING HALT MODE BY USING TEST REQUEST FLAGS
The HALT is released when either or both of the test request flags (INTT RQF and INT0 RQF) are set, and program execution is resumed, starting from the instruction next to the HALT instruction. The contents of the registers and data memory, which have been retained during the HALT mode, are not affected by the release of the HALT mode. 3.5 RELEASING HALT MODE BY USING RESET INPUT
When the RESET signal is input, the HALT mode is unconditionally released, as illustrated in Fig. 3-2.
Fig. 3-2 HALT Mode Release Timing by RESET Input
RESET
HALT mode
Released Ordinary reset operation (execution starts from address 0)
While the RESET signal is active (high level), the HALT mode continues. When the RESET signal goes low, the HALT mode is released. Ordinary resetting operation is then accomplished. Then, the program is executed starting from address 0. The contents of the data memory, retained during the HALT mode, are not affected by the RESET signal. However, the contents of the registers are affected and become undefined.
24
PD7566A, 7566A(A)
4. RESET FUNCTION
The microcomputer is reset and initialized as follows, when an active-high RESET signal is input to the RESET pin: 4.1 INITIALIZATION (1) (2) (3) (4) The program counter (PC9 to PC0) is cleared to 0. The skip flags (SK1 and SK0) for the program status word are reset to 0. The count register for the timer/event counter is cleared to 00H. The clock control circuit is initialized as follows: * Clock mode register (bits CM2 and 1) = 0 CP = CL x 1 256
* Prescalers 1, 2, and 3 = 0 (5) (6) (7) The SM3 flag is reset to 0, disabling the external test input (INT0). The test request flags (INTT RQF and INT0 RQF) are reset to 0. The contents of the data memory and the following registers will become undefined. Stack pointer (SP) Accumulator (A) Carry flag (C) General-purpose registers (H and L) Output latches for ports (8) The output buffers for all the ports are turned off and enter the output high-impedance state. The I/O ports are set in the input mode. Caution When the RESET signal is used to released the standby mode, the contents of the data memory do not become undefined, but are retained. When the RESET signal is removed, the program is executed starting from address 000H. However, initialize or reinitialize the contents for the registers by program.
25
PD7566A, 7566A(A)
5.
INSTRUCTION SET
(1) Operand representation format and description addr caddr caddr1 10-bit immediate data or label 10-bit immediate data or label Immediate data 100H-107H, 140H-147H or label Immediate data 180H-187H, 1C0H-1C7H or label 6-bit immediate data or label 5-bit immediate data or label 4-bit immediate data or label 2-bit immediate data or label 2-bit immediate data or label HL-, HL+, HL
mem n5 n4 n2 bit pr
(2) Legend for "Operation" column A H L HL pr SP PC C PSW CT In Pn Bn Dn Rn (xx) xH : : : : : : : : : : : : : : : : : Accumulator H register L register Pair register (HL) Pair register (HL-, HL+, HL) Stack pointer Program counter Carry flag Program status word Count register Immediate data corresponding to n5, n4, or n2 Immediate data corresponding to addr, caddr, or caddr1 Immediate data corresponding to bit Immediate data corresponding to mem Immediate data corresponding to pr Contents addressed by xx Hexadecimal data
26
PD7566A, 7566A(A)
(3) Selection of port/mode register IPL Instruction L 0 1 AH BH Port Port 0 Port 1 Port 10 Port 11
OPL Instruction L 8 9 AH BH CH FH Port/mode register Port 8 Port 9 Port 10 Port 11 Clock mode register SM3 flag
RPBL; SPBL Instruction L Bit Port FH 3 EH 2 DH 1 CH 0 BH 3 AH 2 9 1 8 0 5 1 4 0 2 2 1 1 Port 8 0 0
Port 11
Port 10
Port 9
(4) Selection of addressing mode by pair register pr HLHL+ HL R1 0 0 1 R0 0 1 0
27
Load/Store
LAI LHI LAM LHLI ST STII
n4 n2 pr n5
0 0 0 1 I3 I2 I1 I0 0 0 1 0 1 0 I1 I0 0 1 0 1 0 0 R1 R0 1 1 0 I4 I3 I2 I1 I0 01010111
A H A H
0 I4, L A
(HL) (HL)
n4
0 1 0 0 I3 I2 I1 I0
n4, L
XAL XAM Arithmetic Operation AISC ASC ACSC pr n4
01111011 0 1 0 1 0 1 R1 R0 0 0 0 0 I3 I2 I1 I0 01111101 01111100
A A A A
L (pr) pr = HL-, HL+, HL A + n4 A + (HL) A + (HL) + C
A, C
EXL
01111110
A
A V (HL)
RC SC ILS IDRS DLS DDRS mem bit bit mem
01111000 01111001 01011001 00111101 01011000 00111100 0 1 1 0 1 0 B1 B0 0 1 1 0 1 1 B1 B0 0 0 D5 D4 D3 D2 D1 D0 0 0 D5 D4 D3 D2 D1 D0
C C L
(mem) L
L-1 (mem) - 1
(mem) (HL)bit (HL)bit
Memory bit Manipulation
RMB SMB
Increment/ Decrement
Accumulator/ Carry Flag Manipulation
CMA
01111111
A
A 0 1 L+1 (mem) + 1
0 1

28
OP Code Instructions Mnemonic operand Operation B1 B2 n4 n2 (pr) pr = HL-, HL+, HL I3-0 Loads n4 to accumulator Loads n2 to register H Loads memory contents addressed by pr to accumulator Loads n5 to registerpair HL Stores accumulator contents to memory addressed by HL L+1 Stores n4 in memory addressed by HL and then increments L register contents Exchanges accumulator contents with L register contents Exchanges accumulator contents with L = FH (HL-) contents of memory addressed by pr L = 0 (HL+) Adds accumulator contents to n4 Adds accumulator contents to contents of memory addressed by HL Adds accumulator contents to contents of memory addressed by HL with carry flag Exclusive-ORs accumulator contents with contents of memory addressed by HL Complements accumulator contents Resets carry flag Sets carry flag Increments L register contents Increments contents of memory addressed by mem Decrements L register contents Decrements contents of memory addressed by mem Resets bit, specified by B1-0, of memory addressed by HL Sets bit, specified by B1-0, of memory addressed by HL L=0 (mem) = 0 L = FH (mem) = FH Carry Carry Carry L = FH (HL-) L = 0 (HL+) String-effect LHLI Skip Condition String-effect LAI
PD7566A, 7566A(A)
OP Code Instructions Jump Mnemonic JMP JCP Subroutine/ Stack Control CALL operand addr addr caddr Operation B1 0 0 1 0 0 0 P9 P8 1 0 P5 P4 P3 P2 P1 P0 0 0 1 1 0 0 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 B2 P7 P6 P5 P4 P3 P2 P1 P0 PC9-0 PC5-0 P9-0 P5-0 Jumps to address indicated by P9-0 Jumps to address specified by P5-0 which replaces PC5-0 Saves contents of PC and PSW to stack, decrements SP by 4, and calls address indicated by caddr Saves contents of PC and PSW to stack, decrements SP by 4, and calls address indicated by caddr1 Restores contents of stack memory to PC and increments SP by 4 Restores contents of stack memory to PC, increments SP by 4, and skips unconditionally Transfers lower 2 bits of accumulator to SP5-4, and higher 3 bits of contents of memory, addressed by HL, to SP3-1 Skips if carry flag is 1 Skips if bit, specified by B1-0, of accumulator is 1 Skips if bit, specified by B1-0, of memory addressed by HL is 1 Skips if bit, specified by B1-0, of memory addressed by HL is 0 Skips if accumulator contents are equal to contents of memory addressed by HL Skips if accumulator contents are equal to n4 Skips if INT RQF is 1, and then clears INT RQF to 0 C=1 Abit = 1 (HL)bit = 1 (HL)bit = 0 A = (HL) Unconditionally Skip Condition
(SP-1)(SP-2)(SP-4) PC9-0 (SP-3) PSW, SP SP - 4 PC9-0 P9-0 (SP-1)(SP-2)(SP-4) PC9-0 (SP-3) PSW, SP SP - 4 PC9-0 0 1 P4P30 0 0 P2P1P0 PC9-0 (SP)(SP+2)(SP+3) SP SP + 4 PC9-0 (SP)(SP+2)(SP+3) SP SP + 4 then skip unconditionally
CAL
caddr1
1 1 1 P4 P3 P2 P1 P0
RT RTS
01010011 01011011
TAMSP
00111111
00110001
Skip
SKC SKABT SKMBT SKMBF SKAEM bit bit bit
01011010 0 1 1 1 0 1 B1 B0 0 1 1 0 0 1 B1 B0 0 1 1 0 0 0 B1 B0 01011111
Skip if C = 1 Skip if Abit = 1 Skip if (HL)bit = 1 Skip if (HL)bit = 0 Skip if A = (HL)
SKAEI SKI
n4 n2
00111111 00111111
0 1 1 0 I3 I2 I1 I0 0 1 0 0 0 0 I1 I0
Skip if A = n4 Skip if INT RQF = 1 Then reset INT RQF
SP5-4 SP3-1
A1-0 (HL)3-1, SP0
0
PD7566A, 7566A(A)
A= n4 INT RQF = 1
29
TCNTAM
00111111
00111011
A CT7-4 (HL) CT3-0 A A Port (L) Port 1 A
Input/Output
IPL IP1 OPL
01110000 01110001 01110010
Port/Mode reg.(L)
RPBL Note SPBL Note CPU Control HALT STOP NOP
01011100 01011101 00111111 00111111 00000000 00110110 00110111
Port bit (L)
Port bit (L) 1 Set Halt mode Set Stop Mode No operation
Note Although the SPBL and RPBL instructions are to set or reset a specified bit, they also output port contents (in 4-bit units) including the specified bit as soon as the specified bit has been set or reset (the contents of the output latch are output to pins other than the specified bit). Before executing these instructions, initialize the contents of the output latch by executing the OPL instruction.

30
OP Code Instructions Mnemonic TIMER operand Operation B1 00111111 B2 00110010 Start Timer Starts timer operation Transfers higher 4 bits of count register to accumulator, and lower 4 bits to memory addressed by HL Loads contents of port specified by L register to accumulator Inputs contents of port to accumulator Outputs accumulator contents to port or mode register specified by L register Resets bits of port 8, 10, or 11 specified by L register Sets bits of port 8, 10, or 11 specified by L register Sets HALT mode Sets STOP mode Performs nothing but waits for 1 machine cycle Skip Condition Timer Control 0
PD7566A, 7566A(A)
PD7566A, 7566A(A)
6. ELECTRICAL SPECIFICATIONS
PD7566A: ABSOLUTE MAXIMUM RATINGS (Ta = 25C)
Item Supply Voltage Symbol VDD Other than ports 10 and 11 Input Voltage VI Ports 10 and 11 Note 1 Note 2 Other than ports 8 to 11 Output Voltage VO Ports 8 to 11 Note 1 Note 2 High-Level Output Current 1 pin IOH Total of all pins Ports 8 and 9 Low-Level Output Current 1 pin IOL Total of all pins Operating Temperature Storage Temperature Power Dissipation Topt Others 15 100 -10 to +70 mA mA C C -15 30 mA mA Condition Rating -0.3 to + 7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +11 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +11 -5 Unit V V V V V V V mA
Tstg Shrink DIP Pd Ta = 70C Mini-flat
-65 to +150 480
mW 250
Note 1. 2.
CMOS input/output or N-channel open-drain output with pull-up resistor connected N-channel open-drain input/output
Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product.
5
31
PD7566A, 7566A(A)
5
PD7566A(A): ABSOLUTE MAXIMUM RATINGS (Ta = 25C)
Item Supply Voltage Symbol VDD Other than ports 10 and 11 Input Voltage VI Ports 10 and 11 Note 1 Note 2 Other than ports 8 to 11 Output Voltage VO Ports 8 to 11 Note 1 Note 2 High-Level Output Current 1 pin IOH Total of all pins Ports 8 and 9 Low-Level Output Current 1 pin IOL Total of all pins Operating Temperature Storage Temperature Power Dissipation Topt Others 15 100 -40 to +85 mA mA C C -15 30 mA mA Condition Rating -0.3 to + 7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +11 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +11 -5 Unit V V V V V V V mA
Tstg Shrink DIP Pd Ta = 85C Mini-flat
-65 to +150 350
mW 195
Note 1. 2.
CMOS input/output or N-channel open-drain output with pull-up resistor connected N-channel open-drain input/output
Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. CAPACITANCE (Ta = 25C, VDD = 0V) Item Input Capacitance Output Capacitance Input/Output Capacitance Symbol CIN COUT f = 1 MHz 0V at pins other than measured pin Condition P00, P01, P10 to P13 Cin0 to Cin3 Ports 8 and 9 Ports 10 and 11 MIN. TYP. MAX. Unit 15 15 35 35 pF pF pF pF
CIO
32
PD7566A, 7566A(A)
OSCILLATOR CHARACTERISTICS PD7566A : Ta = -10 to +70C, VDD = 2.7 to 6.0V
PD7566A(A) : Ta = -40 to +85C, VDD = 2.7 to 6.0V
Oscillator External Circuit Item Condition MIN. TYP. MAX. Unit
VDD = 4.5 to 6.0V
CL1 CL2 R2
290 290 290 290
700 500 400 300
710 510 410 310
kHz kHz kHz kHz
Oscillation frequency (fCC)
VDD = 4.0 to 6.0V VDD = 3.5 to 6.0V VDD = 2.7 to 6.0V After the minimum value of the operating voltage range has been reached
Ceramic Note Oscillator
C1
C2
Oscillation stabilization time (tOS)
20
ms
Note The following ceramic oscillators are recommended: Operating Voltage Range [V] MIN. 2.7 3.5 4.0 4.5 2.7 3.5 4.0 4.5 3.5 4.0 4.5 MAX. 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0
Recommended Constants Manufacturer Product Name C1 [pF] CSB300D CSB400P Murata Mfg. Co., Ltd. CSB500E CSB700A KBR-300B Kyoto Ceramic Co., Ltd. KBR-400B KBR-500B KBR-680B CRK-400 Toko Inc. CRK-500 CRK-680 Caution 1. 2. 100 100 470 330 220 220 120 100 82 100 100 470 330 220 220 120 100 82 6.8 6.8 0 0 0 0 12 12 12 330 220 C2 [pF] 330 220 R2 [k ] 6.8 6.8
Locate the oscillation circuit as close as possible to the CL1 and CL2 pins. Do not route any other signal lines in the area enclosed by the dotted Line.
33
PD7566A, 7566A(A)
PD7566A
DC CHARACTERISTICS
: Ta = -10 to +70C, VDD = 2.7 to 6.0V
PD7566A(A) : Ta = -40 to +85C, VDD = 2.7 to 6.0V
Item Symbol VIH1 High-Level Input Voltage VIH2 Low-Level Input Voltage VIL VDD = 4.5 to 6.0V IOH = -1 mA IOH = -100 A VDD = 4.5 to 6.0V IOL = 1.6 mA Ports 10 and 11 Low-Level Output Voltage VOL VDD = 4.5 to 6.0V IOL = 10 mA IOL = 400 A VDD = 4.5 to 6.0V IOL = 15 mA IOL = 600 A ILIH1 High-Level Input Leakage Current ILIH2 Low-Level Input Leakage Current ILIL ILOH1 High-Level Output Leakage Current ILOH2 Low-Level Output Leakage Current Resistor Interconnected To Input Pin (Pull-Up, Pull-Down) Resistor Interconnected To Output Pin (Pull-Up) ILOL VOUT = 9V, Ports 8, 9, 10 and 11 VOUT = 0V
Note 1
Condition Other than ports 10 and 11 Ports 10 and 11Note 1
MIN. 0.7VDD 0.7VDD 0 VDD-2.0 VDD-1.0
TYP.
MAX. VDD 9 0.3VDD
Unit V V V V V
High-Level Output Voltage
VOH
Ports 8 to 11
0.4
V
2.0 0.5 2.0 0.5 3 10 -3 3 10 -3
V V V V
Port 8 and 9
VIN = VDD VIN = 9V, Ports 10 and 11Note 1 VIN = 0V VOUT = VDD
A A A A A A
k
Ports 0 and 1, RESET
23.5
47
70.5
Ports 10 and 11 VDD = 5V+10% fCC = 700 kHz IDD1 Operation mode VDD = 3V+10% fCC = 300 kHz
7.5
15
22.5
k
650
2200
A A A A A A
120
360
Supply CurrentNote 2 IDD2 HALT mode
VDD = 5V+10% fCC = 700 kHz VDD = 3V+10% fCC = 300 kHz VDD = 5V+10% IDD3 STOP mode VDD = 3V+10%
450
1500
65 0.1 0.1
200 10 5
Note 1. With N-channel open-drain input/output selected 2. Excluding current flowing through internal pull-up and pull-down resistors, comparator, and internal bias resistor
34
PD7566A, 7566A(A)
COMPARATOR CHARACTERISTICS PD7566A : Ta = -10 to +70C, VDD = 3.0 to 6.0V
PD7566A(A) : Ta = -40 to +85C, VDD = 3.0 to 6.0V
Item Ccomparator Current Note Dissipation Input Voltage Range Response Time Comparator Input Resolution Input Leakage Current Internal Bias Resistor Rref 50 100 VDD =5V10% Vcin Vref Symbol Condition Cin 0 to Cin 3, 1 circuit VDD = 5V10% MIN. TYP. MAX. Unit
25
50
100
A
5
0 2 10
VDD 4 50 100 3 200
V tCY mV mV
A
k
5
Note Excluding current flowing through internal bias resistor AC CHARACTERISTICS
PD7566A
: Ta = -10 to +70C, VDD = 2.7 to 6.0V
PD7566A(A) : Ta = -40 to +85C, VDD = 2.7 to 6.0V
Item Internal Clock Cycle Time Symbol tCY
Note
Condition VDD =4.5 to 6.0V
MIN. 2.8 6.4
TYP.
MAX. 6.9 6.9 710 350 0.2
Unit
s s
kHz kHz
P00 Event Input Frequency P00 Input Rise and Fall Time P00 Input High- and Low-Level Widths INT0 High- and Low-Level Widths Reset High- and Low-Level Widths
fP0 tP0R, tP0F tP0H, tP0L tI0H, tI0L tRSH, tRSL
duty = 50%
VDD = 4.5 to 6.0V
0 0
s s s s s
VDD = 4.5 to 6.0V
0.7 1.45 10 10
Note tCY = 2/fCC (Refer to the characteristic curve for the power requirement not listed above.) AC TIMING MEASURING POINTS (other than CL1 input)
0.7 VDD 0.3 VDD
Measuring points
0.7 VDD 0.3 VDD
35
PD7566A, 7566A(A)
PD7566A
DATA MEMORY DATA RETENTION CHARACTERISTICS IN STOP MODE
: Ta = -10 to +70C
PD7566A(A): Ta = -40 to +85C
Item Supply Voltage for Data Retention Supply Current for Data Retention Reset Setup Time Oscillation Stabilization Time Symbol VDDDR IDDDR tSRS tOS After VDD reached 4.5V VDDDR = 2.0V 0 20 Condition MIN. 2.0 0.1 TYP. MAX. 6.0 5 Unit V
A s
ms
DATA RETENTION TIMING
HALT mode Operation mode
STOP mode Data retention mode VDD VDDDR tSRS STOP instruction is carried out RESET
tOS
36
PD7566A, 7566A(A)
CLOCK TIMING
1/fC tCL tCH
CL1 input
tCR
tCF
1/fP0 tP0L tP0H
P00 input
tP0R
tP0F
TEST INPUT TIMING
tI0L
tI0H
INT0
RESET INPUT TIMING
tRSL
tRSH
RESET
37
PD7566A, 7566A(A)
7.
CHARACTERISTIC DATA
fCC vs. VDD Guaranteed Operation Range PD7566A : T a = -10 to +70 C PD7566A(A) : T a = -40 to +85 C
System clock oscillation frequency fCC [kHz]
1000 50
CL1 CL2 R2 C1 C2
Guaranteed operation range
100
0
1
2
3
4
5
6
Supply voltage V DD [V]
fPO vs. VDD Guaranteed Operation Range PD7566A : T a = -10 to +70 C PD7566A(A) : T a = -40 to +85 C
t1 t2
P00 event input frequency fPO [kHz]
1000 500
t1>t2:fx= 1 2t2 t1Guaranteed operation range 100
10 0 1 2 3 4 5 6 Supply voltage V DD [V]
38
PD7566A, 7566A(A)
IDD vs. VDD Characteristic Example (Reference Value) (Ta = 25C)
CL1
330 pF
CL2
CL1
CL2
6.8 k 100 fcc = 700 kHz pF Operation mode
1000 Supply current IDD [A] 500
6.8 k 330 100 pF pF
CSB300D
CSB700A
HALT mode
fcc = 300 kHz Operation mode 100 50 HALT mode
10
0
1
2
3
4
5
6
Supply voltage VDD [V]
IOL vs. VOL Characteristic Example (Ports 8 and 9) (Reference Value) (Ta = 25C) 30 Low-level output current I0L [mA]
25 VDD = 5 V 20
15 VDD = 3 V 10 Caution The absolute maximum rating is 30 mA per pin.
5 0
0
1
2
3
4
5
6
Low-level output voltage V0L [V]
39
PD7566A, 7566A(A)
IOL vs. VOL Characteristic Example (Ports 10 and 11) (Reference Value) (Ta = 25C) 30 Low-level output current I0L [mA]
25
20 VDD = 5 V
15
10
VDD = 3 V
Caution The absolute maximum rating is 15 mA per pin.
5 0
0
1
2
3
4
5
6
Low-level output voltage V0L [V]
IOH vs. VOH Characteristic Example (Reference Value) (Ta = 25C)
High-level output current I0H [mA]
-5
VDD = 5 V
-4
-3
-2 VDD = 3 V -1 0
Caution The absolute maximum rating is -5 mA per pin.
0
1
2
3
4
5
6
VDD - V0H [V]
40
PD7566A, 7566A(A)
8. APPLICATION CIRCUITS
(1) Refrigerator and Air Conditioner
LEDx4 AC03DGM, etc.
AC16DGM, etc. 9V MAX. Cin0 Cin1 AC100V + RD 5.1E + Cin2 Cin3 Comparator inputs RES P80 P81 P82 P90 P91
Thermistors Vref P100 P101 P102
PD7566A
(Pull-down resistor interconnected) 2SA733 INT0 CMOS output P110 Input with pull-up resistor interconnected P111 P112 Switch input (door switch)
P103 CL1 CL2
The above example shows a circuit for a refrigerator. A circuit for an air conditioner can be implemented by replacing only the heater with a fan motor.
Compressor motor Overcurrent detector
Heater
P113 (CMOS output)
2SC945A
41
PD7566A, 7566A(A)
(2) Rice Cooker
2SA733
LED x4
RD + 10E RES P80 P81 P82 P90 P91
AC03DGM, etc.
AC100 V P110 Vref CMOS output P100 P101 P102 P103
PD7566A
P112 CMOS outputs Inputs with pull-down resistor interconnected P00 P11 P12 P13 BZ Piezoelectric buzzer
CL1
CL2
42
Heater for cooking
Cin 0 Comparator input
P111
RD 24E
Heater for temperature control
RD 5.1E
Open-drain outputs
RL
+
PD7566A, 7566A(A)
(3) Washing Machine
2SA733
AC0V8DGM AC03DGM etc. etc. RES P90 P91 Open-drain P100 P101
2SC945A x2
AC08DGM etc.
P102 (open-drain input) + RD 5.6E
Water supply magnet
M Drainage magnet Motor
AC100V
+
CMOS outputs
P110 to P113
Driver PA80C
PD7566A
LEDx12 P103 (CMOS output) Piezoelectric buzzer BZ Inputs with pull-up resistor interconnected Open-drain outputs P80 P81 P82 P10 P11 P12 P13 CL2 Input 12 keys
P00 P01
CL1
43
PD7566A, 7566A(A)
(4) Cassette Deck Controller
PD7566A
P91 Motor plunger driver P100 P101 3 P110-P112 2SA733 LED x8
Recording signal Mute signal Leader signal
P113 P102 Inputs with pull-up resistor interconnected Open-drain outputs P103
P80 P81 P82 P90 P10 P11 P12 CL2 12 keys
Tape end detection Pause input Voltage detection
INT0 P01 P13
CL1
44
PD7566A, 7566A(A)
(5) Remote Controller
PD7566A
P80 (CMOS Output) RESET (with pull-down resistor interconnected) P00 P01 P10 P11 Inputs with pull-up resistor interconnected P12 P13 P100 P101 P102 P103 70 keys max. 2SA733
P82 P90 N-channel, open-drain output P91 P110 P111 P112 P113
P81 CL1 CL2
2SA952
Ceramic oscillator 304 kHz
Infrared light-emitting diode SE307-C
45
PD7566A, 7566A(A)
9.
PACKAGE DRAWINGS
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (1/2)
24 PIN PLASTIC SHRINK DIP (300 mil)
24 13
1 A I
12
K L
J
G H
F D N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 23.12 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.85 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 7.62 (T.P.) 6.5 0.25 +0.10 -0.05 0.17 0~15
INCHES 0.911 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.033 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.300 (T.P.) 0.256 0.010 +0.004 -0.003 0.007 0~15 S24C-70-300B-1
5
Caution Dimensions of ES products are different from those of mass-production products. Refer to DRAWINGS OF ES PRODUCT PACKAGES (1/2).
46
PD7566A, 7566A(A)
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (2/2)
24 PIN PLASTIC SOP (300 mil)
24 13 detail of lead end
1 A
12 H
G
P I
J
F
K
E
C D M
M
N
B
L
NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 15.54 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 -0.05 0.10.1 1.8 MAX. 1.55 7.70.3 5.6 1.1 0.20 +0.10 -0.05 0.60.2 0.12 0.10 3 +7 -3
INCHES 0.612 MAX. 0.031 MAX. 0.050 (T.P.) 0.016 +0.004 -0.003 0.0040.004 0.071 MAX. 0.061 0.3030.012 0.220 0.043 0.008 +0.004 -0.002 0.024 +0.008 -0.009 0.005 0.004 3 +7 -3 P24GM-50-300B-4
Caution Dimensions and materials of ES products are different from those of mass-production products. Refer to DRAWINGS OF ES PRODUCT PACKAGES (2/2).
5
47
PD7566A, 7566A(A)
DRAWINGS OF ES PRODUCT PACKAGES (1/2) ES 24 PIN SHRINK DIP (REFERENCE) (UNIT: mm)
48
PD7566A, 7566A(A)
DRAWINGS OF ES PRODUCT PACKAGES (2/2) ES 24 PIN CERAMIC SOP (REFERENCE) (UNIT: mm)
49
PD7566A, 7566A(A)
10.
RECOMMENDED PC BOARD PATTERN FOR SOP (REFERENCE) (UNIT:
7.62
mm)
0.51
1.27
* The pattern shown above conforms to the Integrated Circuit Dimensions Rule (IC-74-2) stipulated by the Electric Industry Association of Japan (EIAJ). * The dimensions of this pattern are applicable to all the products called flat DIP (mini-flat) "form A 300 mil type". * If there is a possibility that solder bridges could be formed, shorten the pitch (0.76 mm) between pads, without changing the length for each pad (1.27 mm).
50
0.76
1.27
PD7566A, 7566A(A)
11. RECOMMENDED SOLDERING CONDITIONS 5
For the PD7566A, soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document "Semiconductor device mounting technology manual" (IEI-1207). For other soldering methods, please consult with NEC sales personnel. Table 11-1 Soldering Conditions of Surface Mount Type
PD7566AG-XXX: 24-pin plastic SOP (300 mil) PD7566AG(A)-XXX: 24-pin plastic SOP (300 mil)
Recommended Conditions Reference Code IR30-00-1
Soldering Method
Soldering Conditions
Infrared Reflow
Package peak temperature 230C, Time: 30 secondes max. (210C min.), Number of soldering operations: 1, Package peak temperature 215C, Time: 40 seconds max. (200C min.), Number of soldering operations: 1 Solder bath temperature: 260C max., Time: 10 seconds max., Preparatory heating temperature: 120C max. (Package surface temperature) Pin temperature: 300C max., Time: 3 seconds max. (Per side)
VPS
VP15-00-1
Wave Soldering
WS60-00-1
Pin Partial Heating
-
Caution Do not use one soldering method in combination with another (however, pin partial heating can be performed with other soldering methods). Table 11-2 Soldering Conditions of Through-Hole Type
PD7566ACS-XXX: 24-pin plastic shrink DIP (300 mil) PD7566ACS(A)-XXX: 24-pin plastic shrink DIP (300 mil)
Soldering Method Wave Soldering (Only for pin part) Pin Partial Heating Soldering Conditions Solder bath temperature: 260C max., Time: 10 seconds max.
Pin temperature: 300C max., Time: 3 seconds max. (Per pin)
Caution The wave soldering must be performed at the pin part only. Note that the solder must not be directly contacted to the package body.
51
5
52
APPENDIX A.
Product Item Instruction Cycle/System Clock (5 V) Ceramic Instruction Set ROM RAM I/O Ports Total Port 0 Port 1 Port 8 RC External
PD7556
PD75P56
PD7556A PD7556A(A)
PD7566
PD75P66
- -
PD7566A
PD7566A(A)
4 s/500 kHz 2.86 s/700 kHz - 45 (SET B) 1024 x 8 64 x 4 20 P00, P01 P10-P13 P80-P82, P83/CL2 12 V 14 or 15 P00 - P80-P82, P83(CL2) 20 P00, P01 P10-P13 P80-P82, P83/CL2 9V 12 V 19 P00, P01 P10-P13 14 P00 -
2.86 s/700 kHz
COMPARISON FOR PD7566A SUB-SERIES PRODUCTS
19 P00, P01 P10-P13 P80-P82
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Breakdown Voltage Limit Port 9, 10, 11 Breakdown Voltage Limit Timer/Event Counter Comparator Supply Voltage Range Package 2.5-6.0 V
9V
P90, P91, P100-P103, P110-P113 12 V 9V 12 V 9V
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 bits 4 channels 4.5-6.0 V 2.0-6.0 V 2.7-6.0 V 2.7-6.0 V 4.5-6.0 V 2.7-6.0 V 2.7-6.0 V
PD7566A, 7566A(A)
24-pin plastic shrink DIP 24-pin plastic SOP
PD7566A, 7566A(A)
APPENDIX B. DEVELOPMENT SUPPORT TOOLS
The following development support tools are available for developing a system in which the PD7566A is employed. Language Processor This absolute assembler is a program which converts a program written in mnemonic to object code, so that it can be executed by microcomputer. In addition, this absolute assembler is provided with a function which automatically performs branch instruction optimization.
PD7550, 7560 Series Absolute Assembler
Host machine OS PC-9800 series MS-DOS Ver.3.10 to Note Ver.5.00A PC DOS (Ver.3.1 )
TM TM
Media 3.5"2HD 5.25" 2HD 5.25" 2HC
Order code (Product name)
S5A13AS7554 S5A10AS7554 S7B10AS7554
IBM PC/AT
TM
PROM Programming Tool PROM programmer that can easily program typical PROMs of 256K to 4M bits or single-chip microcomputers with built-in PROMs in the stand-alone mode or remotely from the host machine by connecting the accessory boards and separately sold program adapters. PROM programmer adapter to be connected to the PG-1500 for programming the PD75P56 or the PD75P66. Allows controlling the PG-1500 connected to the host machine via the serial and parallel interface, from the host machine. Host machine OS Software PG-1500 Controller PC-9800 series MS-DOS Ver.3.10 to Note Ver.5.00A PC DOS (Ver.3.1 ) Media 3.5"2HD 5.25" 2HD 5.25" 2HC Order code (Product name)
PG-1500 Hardware PA-75P56CS
S5A13PG1500 S5A10PG1500 S7B10PG1500
IBM PC/AT
Note Although Ver. 5.00/5.00A is provided with a task swap function, this function cannot be used with this software. Remark The operations of the assembler and PG-1500 controller are guaranteed only on the above host machine and OS.
53
PD7566A, 7566A(A)
Debugging Tool The EVAKIT-7500B is an evaluation board which can be used commonly with the PD7500 series products. For system development with the PD7566A, the and the EV-7554A option EVAKIT-7500B board are used together. EVAKIT-7500B Although the EVAKIT-7500B can operate in the stand-alone mode, the EVAKIT-7500B has 2 serial interface channels on its board to which a console, such as RS-232C, etc., can be connected for debugging. Additionally, the EVAKIT-7500B has real-time tracing function, so that the conditions of the program counter and the output ports can be traced on a real-time basis. The EVAKIT-7500B also has a PROM programmer for effective debugging. EV-7554A SE-7554A The EV-7554A is used together with the EVAKIT-7500B to evaluate the PD7566A. The SE-7554A is a simulation board for evaluating a system by mounting the program, developed by the EVAKIT-7500B, in place of the PD7566A. The EVAKIT-7500 control program controls the EVAKIT-7500B from the host machine by connecting the EVAKIT-7500B to the host machine via the RS-232C. EVAKIT-7500 Control Program (EVAKIT controller) Host machine OS PC-9800 series MS-DOS Ver.3.10 to Note Ver.5.00A PC DOS (Ver.3.1 ) Media 3.5"2HD 5.25" 2HD 5.25" 2D Order code (Product name)
Hardware
Software
S5A13EV7500-P01 S5A10EV7500-P01 S7B11EV7500-P01
IBM PC series
Note Although Ver. 5.00/5.00A is provided with a task swap function, this function cannot be used with this software.
5
Caution It is not possible to internally mount a pull-up resistor in a port in the EVAKIT-7500B. When evaluating, arrange to have a pull-up resistor mounted in the user system. Remark Operations of the EVAKIT controller are guaranteed on the above listed host machines with the listed operating system.
54
PD7566A, 7566A(A)
APPENDIX C. RELATED DOCUMENTS
DOCUMENT RELATED TO DEVICE Document Name User's Manual Document No. IEU-1111D IF-1027G
5
PD7500-series Selection Guide
DOCUMENT RELATED TO DEVELOPMENT TOOL Document Name EVAKIT-7500B User's Manual Hardware EV-7554A User's Manual PG-1500 User's Manual Document No. EEU-1017C EEU-1034A EEU-1335B EEM-1006 EEM-1356 EEM-1049 EEU-1291B
PD7550, 7560-series Abusolute Assembler User's Manual
Software EVAKIT-7500 Control Program User's Manual MS-DOS base PC DOS base PG-1500 Controller User's Manual
OTHER RELATED DOCUMENT Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Static Electricity Discharge (ESD) Guarantee Guide Semiconductor Device Quality Guarantee Guide Microcomputer-Related Product Guide -Third Party Product Document No. IEI-1213 IEI-1207 IEI-1209A IEI-1203A IEI-1201 MEI-1202 Note
Remark These documents above are subject to change without notice. Be sure to use the latest document for designing. Note To be published.
55
PD7566A, 7566A(A)
[MEMO]
56
PD7566A, 7566A(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
57
PD7566A, 7566A(A)
[MEMO]
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation.

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